The present invention relates generally to the fields of digital circuitry and electronics. More particularly, it relates to an input buffer circuit suitable for receiving signals in accordance with multiple differential I/O standards having different input operating rangesxe2x80x94e.g., the LVDS standard and another differential standard such as CML or PCML.
Digital electronic systems are commonly implemented by combining and interconnecting several different integrated circuit (IC) devices such as processors, memory devices and programmable logic devices. The various IC devices communicate with one another by way of input and output (I/O) signals transmitted over a system bus, and several different I/O standards exist for this purpose. One prevalent I/O standard is Low Voltage Differential Signaling (LVDS). LVDS is a low noise, low power, and high-speed I/O interface that uses differential signals without a reference voltage and therefore requires two signal lines for each signal channel. The voltage difference between the two signal lines defines the logic state of the LVDS signal.
Generally, an LVDS output driver in a transmitting device converts a single-ended digital logic signalxe2x80x94e.g., a CMOS (Complementary Metal Oxide Semiconductor) or TTL (Transistorxe2x80x94Transistor Logic) logic level signalxe2x80x94into the LVDS differential format. The differential signal generated by an LVDS output driver has a typical voltage swing of about 350 mV and a typical common-mode voltage of about 1.2 V on the two LVDS signal lines. The small voltage swing in the LVDS signal makes the standard well-suited for high-speed data transmission. From the output driver, the LVDS signals are transmitted to another device having an LVDS receiver for converting the differential signal back into a desired single-ended logic signal format. The LVDS receiver includes an input buffer circuit powered by an I/O supply voltage VCC. The VCC I/O supply typically equals 3.3 V, however the voltage swing in the LVDS standard is not dependent on power supply levels. Generally, the LVDS receiver must be able to tolerate axc2x11 V shift between the ground reference of the output driver and the receiver ground. Therefore, where the LVDS signal provided by an output driver swings from 1.0-1.4 V, the LVDS input buffer must be able to operate properly with input voltage swings that range from 0.0-0.4 V in the case of axe2x88x921 V ground shift, to 2.0-2.4 V for a+1 V ground shift. Therefore, the LVDS input buffer has an input operating range from 0.0-2.4 V.
Since many differential I/O standards, including LVDS, are commonly used in digital systems, it is advantageous if an input buffer circuit is compatible with and able to support multiple differential I/O standards. In particular, it is often desirable for the input buffer circuit of an LVDS receiver to be able to properly receive and process signals formatted according to other differential I/O standards. However, for some other differential I/O standards, such as the CML (current mode logic) and PCML (pseudo current mode logic) standards, the input operating range is designed to be at or near the VCC voltage level. For example, in the CML standard, the input voltage may swing from 0.6 V below VCC to VCC. Where VCC=3.3. V, the CML input operating range is from 2.7-3.3 V. Unfortunately, however, the differential amplifier circuitry in existing LVDS input buffer circuits generally does not respond well to input voltages that are higher than 2.4 V and therefore outside the LVDS operating range.
Consequently, there is a need for an input buffer circuit that is compatible with differential input signals for different digital I/O standards, even when the input voltage operating ranges for the different standards vary. In addition, there is a more specific need for an input buffer circuit that fully supports both LVDS and other differential I/O standard signals such as CML and PCML signals. Furthermore, it would be especially desirable to provide an input buffer circuit, originally designed for one I/O standard, that is readily adapted to support other I/O signal standards while still using a significant part of the original input buffer circuitry.
The present invention provides an input buffer circuit having a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. By selectively enabling, in a given input buffer mode, only the differential amplifier circuit(s) configured for a specific input signal standard, the input buffer provides considerable flexibility in interfacing between digital devices using a variety of differential I/O standards. If the input operating range for an I/O standard is largexe2x80x94as is the case for LVDS and LVPECL xe2x80x94two or more differential amplifier circuits can be used to provide amplification in different portions of the input operating range. The selective enabling/disabling of differential amplifier circuits may be performed by one or more programmable control signals. By sharing current source and other input buffer circuitry in each differential I/O standard operating mode, unnecessary duplication of circuit functions in the input buffer is also avoided.
In one embodiment, the invention provides an input buffer circuit having first and second differential input terminals for receiving first and second input signals respectively. The difference between the input signals provides a differential input signal. A first differential amplifier circuit has a first input coupled to the first differential input terminal and a second input coupled to the second differential input terminal. The first differential amplifier circuit is configured to generate a first logic level signal at an output node when the differential input is provided in accordance with a first digital I/O standard. Similarly, a second differential amplifier circuit has a first input coupled to the first differential input terminal and a second input coupled to the second differential input terminal. The second differential amplifier circuit is configured to generate a second logic level signal at the output node when the differential input is provided in accordance with a second digital I/O standard. To selectively enabling the first differential amplifier circuit in a first input buffer mode, a first set of one or more switch circuits coupled to the first differential amplifier circuit may be used. To selectively enabling the second differential amplifier circuit in a second input buffer mode, a second set of one or more switch circuits coupled to the second differential amplifier circuit may be used.
Where the first digital I/O standard has a wide input operating range, the first differential amplifier circuit may be configured to generate the first logic level signal at the output node when the differential input is provided in accordance with the first digital I/O standard and a common mode component of the input signals is in a first, e.g., upper, portion of the input operating range. In this case the input buffer circuit may also include a third differential amplifier circuit having a first input coupled to the first differential input terminal and a second input coupled to the second differential input terminal. The third differential amplifier circuit is configured to generate the first logic level signal at the output node when the differential input is provided in accordance with the first digital I/O standard and the common mode component of the input signals is in a second, e.g., lower, portion of the first I/O standard""s input operating range. Here, a third set of one or more switch circuits coupled to the third differential amplifier circuit may be used to selectively enable the third differential amplifier circuit in the first input buffer mode.